[Mark] starts a post from a bit ago with: “… maybe you have also heard that SystemVerilog is simply an extension of Verilog, focused on testing and verification.” This is both true and false, depending on how you look at it. [Mark] then explains what the differences are. It’s a good read if you are Verilog fluent, but just dip your toe into SystemVerilog.

Part of the confusion is that until 2009, there were two different things: Verilog and SystemVerilog. However, the SystemVerilog 2009 specification incorporates both languages, so modern Verilog is SystemVerilog and vice versa.

While many new features are aimed at verification, there is something for everyone. For example, [Mark] explains how you can replace instances of reg and wire with the logic data type. SystemVerilog will figure out if you need a reg or a wire on its own.

In addition, some common idioms are now part of the standard, which can make defining always blocks easier. So if you are using FPGAs and Verilog, are you using SystemVerilog? We don’t see much of it in incoming projects, but we do see it occasionally. Of course, pundits tell us that soon we won’t even have to write Verilog thanks to — what else? — AI. We remain skeptical.